The present invention relates generally to integrated circuit manufacture and specifically to test methods and test structures for evaluating electrical characteristics of interconnects used in semiconductors.
In integrated circuit (IC) technologies, contact resistance can be effected by the geometry of the metal levels present in the circuit due to a variety of physical effects. For example, the misalignment of vias with respect to small metal features, resist pull back from the edge of large metal features, dielectric thickness variations due to local and extended topography, and small metal features printing smaller than intended all may affect contact resistance. Circuit performance and life is dependent upon predictable and constant performance with regard to resistance and capacitance. Therefore, variation in the resistance can adversely affect the entire circuit and cause integrated circuit failure. To monitor the circuit, integrated circuits often contain self-monitoring capabilities to detect abnormalities or non-uniformity in terms of capacitance and resistance. However, even slight variations, which are difficult to detect, can result in circuit failure over time. Unfortunately, present integrated measurement techniques are not able to quantify small anomalies and irregularities in contact resistance.
There are two standard methods of measuring contact resistance between conductor levels. First, there is the so-called xe2x80x9cchainxe2x80x9d method of testing many contacts and series. Another useful measurement technique is known as the Kelvin contact resistance measurement.
Contact chains always have excess resistance in the series which masks the effect being studied to a certain degree. Kelvin contact resistance measurements measure the contact resistance without adverse effects of series resistance (chain method). However, the Kelvin contact resistance technique has special geometry considerations which limit the technique from being used with certain studies.
In one embodiment, the present invention relates to a method for measuring contact resistance between conductors in an integrated circuit using upper and lower Kelvin contact resistance conductors and further comprising an intermediate metal layer positioned between the upper and lower Kelvin conductors.
In a further embodiment, the present invention relates to a Kelvin resistance test structure in an integrated circuit used to measure contact anomalies in multi-level metal integrated circuits. The test structure comprises conventional Kelvin contact resistance conductors above and below the interconnect being tested, along with a new metal layer positioned between the first and second metal pad connectors.
In a still further embodiment, the present invention is directed to a method for measuring contact resistance of an interconnect in a semiconductor. Upper and lower Kelvin contact resistance conductors are provided within substrates, with a novel intermediate conductor positioned horizontally between the two Kelvin conductors.
In still a further embodiment, the present invention is directed to a semiconductor having an interconnect comprising a substrate having a via extending there through. The via contacts upper and lower Kelvin contact resistance conductors, and a third intermediate conductor located vertically between the upper and lower Kelvin contact resistance conductors to measure contact resistance.